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ispLSI 2064E
In-System Programmable SuperFASTTM High Density PLD Features
* SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC -- 2000 PLD Gates -- 64 I/O Pins, Four Dedicated Inputs -- 64 Registers -- High Speed Global Interconnect -- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. -- Small Logic Block Size for Random Logic -- 100% Functionally and JEDEC Upward Compatible with ispLSI 2064 Devices * HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- fmax = 200 MHz Maximum Operating Frequency -- tpd = 4.5 ns Propagation Delay -- TTL Compatible Inputs and Outputs -- 5V Programmable Logic Core -- ispJTAGTM In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port -- User-Selectable 3.3V or 5V I/O Supports Mixed Voltage Systems -- PCI Compatible Outputs -- Open-Drain Output Option -- Electrically Erasable and Reprogrammable -- Non-Volatile -- Unused Product Term Shutdown Saves Power * ispLSI OFFERS THE FOLLOWING ADDED FEATURES -- Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality -- Reprogram Soldered Devices for Faster Prototyping * OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS -- Complete Programmable Device Can Combine Glue Logic and Structured Designs -- Enhanced Pin Locking Capability -- Three Dedicated Clock Input Pins -- Synchronous and Asynchronous Clocks -- Programmable Output Slew Rate Control to Minimize Switching Noise -- Flexible Pin Placement -- Optimized Global Routing Pool Provides Global Interconnectivity * ispDesignEXPERTTM - LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING -- Superior Quality of Results -- Tightly Integrated with Leading CAE Vendor Tools -- Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZERTM -- PC and UNIX Platforms
(R)
Functional Block Diagram
Input Bus
Output Routing Pool (ORP) B7 B6 B5 B4
A0
Output Routing Pool (ORP)
Input Bus
A2
GLB
Logic Array
DQ
DQ
B1
DQ
A3 A4 A5 A6 A7
B0
Output Routing Pool (ORP)
Input Bus
0139/2064E
Description
The ispLSI 2064E is a High Density Programmable Logic Device. The device contains 64 Registers, 64 Universal I/O pins, four Dedicated Input Pins, three Dedicated Clock Input Pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2064E features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 2064E offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2064E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. B7 (see Figure 1). There are a total of 16 GLBs in the ispLSI 2064E device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device.
Copyright (c) 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
June 2000
2064e_05
1
Input Bus
A1
DQ
B2
Output Routing Pool (ORP)
Global Routing Pool (GRP)
B3
Specifications ispLSI 2064E
Functional Block Diagram
Figure 1. ispLSI 2064E Functional Block Diagram
GOE 0 GOE 1 I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48
Input Bus
Generic Logic Blocks (GLBs)
Megablock
B7
Output Routing Pool (ORP)
B6 B5 B4
Output Routing Pool (ORP)
I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 TDI/IN 0 TMS/IN 1
Input Bus
Input Bus
I/O 4 I/O 5 I/O 6 I/O 7
Output Routing Pool (ORP)
I/O 0 I/O 1 I/O 2 I/O 3
I/O 47
A0
B3
I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 TCK/IN 3 TDO/IN 2
A1
Global Routing Pool (GRP)
B2
A2
B1
A3
B0
A4
A5
A6
A7
BSCAN
Input Bus
I/O 16 I/O 17
I/O 18 I/O 19
I/O 20 I/O 21 I/O 22 I/O 23
I/O 24 I/O 25 I/O 26 I/O 27
I/O 28 I/O 29 I/O 30 I/O 31
The device also has 64 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, output or bidirectional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. By connecting the VCCIO pins to a common 5V or 3.3V power supply, I/O output levels can be matched to 5V or 3.3V compatible voltages. When connected to a 5V supply, the I/O pins provide PCI-compatible output drive. Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by two ORPs. Each ispLSI 2064E device contains two Megablocks. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 2064E device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the outputs of the ispLSI 2064E are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the ispDesignEXPERT software tools.
2
Y0 Y1 Y2
CLK 0 CLK 1 CLK 2
0139B(1)isp/2064E
RESET
Output Routing Pool (ORP)
Specifications ispLSI 2064E
Absolute Maximum Ratings 1
Supply Voltage Vcc ................................................... -0.5 to +7.0V Input Voltage Applied .............................. -2.5 to VCC +1.0V Off-State Output Voltage Applied ........... -2.5 to VCC +1.0V Storage Temperature ..................................... -65 to 150C Case Temp. with Power Applied .................... -55 to 125C Max. Junction Temp. (TJ) with Power Applied ............ 150C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL PARAMETER Supply Voltage: Logic Core, Input Buffers Supply Voltage: Output Drivers Input Low Voltage Input High Voltage 5V 3.3V TA = 0C to +70C MIN. 4.75 4.75 3.0 0 2.0 MAX. 5.25 5.25 3.6 0.8 Vcc+1 UNITS V V V V V
Table 2-0005/2096E
VCC VCCIO VIL VIH
Capacitance (TA=25C, f=1.0 MHz)
SYMBOL PARAMETER Dedicated Input Capacitance I/O Capacitance Clock Capacitance TYPICAL 8 8 10 UNITS pf pf pf TEST CONDITIONS VCC = 5.0V, VIN = 2.0V VCC = 5.0V, VI/O = 2.0V VCC = 5.0V, VY = 2.0V
Table 2-0006/2064e
C1 C2 C3
Erase/Reprogram Specification
PARAMETER Erase/Reprogram Cycles MINIMUM 10,000 MAXIMUM - UNITS Cycles
Table 2-0008/2064e
3
Specifications ispLSI 2064E
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to 3.0V 1.5 ns 1.5V 1.5V See Figure 2
Table 2-0003/2064E
Figure 2. Test Load
+ 5V R1 Device Output R2 C L* Test Point
Output Load Conditions (see Figure 2)
TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL +0.5V R1 470 470 470 R2 390 390 390 390 390 CL 35pF 35pF 35pF 5pF 5pF
*CL includes Test Fixture and Probe Capacitance.
C
Table 2-0004/2064
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current IOL = 8 mA IOH = -4 mA 0V VIN VIL (Max.) (VCCIO - 0.2)V VIN VCCIO VCCIO VIN 5.25V 0V VIN 2.0V VCCIO = 5.0V or 3.3V, VOUT = 0.5V VIL = 0.0V, VIH = 3.0V fTOGGLE = 1 MHz CONDITION MIN. - 2.4 - - - -10 - - TYP.3 - - - - - - - 100 MAX. UNITS 0.4 - -10 10 10 -250 -240 - V V A A A A mA mA
VOL VOH IIL IIH IIL-PU IOS1 ICC2,4,5
Table 2-0007/2064E 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using four 16-bit counters. 3. Typical values are at VCC = 5V and TA = 25C. 4. Unused inputs held at 0.0V. 5. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC.
4
Specifications ispLSI 2064E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST 2 4# COND. A A A - - - A - - - - A - B C B C - - DESCRIPTION1 -200 - - 200
1 tsu2 + tco1
-135 - - 135 100 143 5.0 - 0.0 6.0 - 0.0 - 5.0 - - - - 3.5 3.5 7.5 10.0 - - - - 4.0 - - 4.5 - 10.0 - 12.0 12.0 7.0 7.0 - - - -
-100 10.0 13.0 - - - - 5.0 - - 6.0 - 13.5 - 15.0 15.0 9.0 9.0 - -
MIN. MAX. MIN. MAX. MIN. MAX. 4.5 7.0 - - - - 3.0 - - 3.5 - 6.0 - 8.0 8.0 4.0 4.0 - -
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl
1. 2. 3. 4.
1 Data Prop Delay, 4PT Bypass, ORP Bypass 2 Data Prop Delay 3 Clk Freq with Internal Feedback3 4 Clk Freq with External Feedback ( 5 Clk Frequency, Max. Toggle 6 GLB Reg Setup Time before Clk, 4 PT Bypass 7 GLB Reg Clk to Output Delay, ORP Bypass 8 GLB Reg Hold Time after Clk, 4 PT Bypass 9 GLB Reg Setup Time before Clk 10 GLB Reg Clk to Output Delay 11 GLB Reg Hold Time after Clk 12 External Reset Pin to Output Delay 13 External Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable 18 External Synch Clk Pulse Duration, High 19 External Synch Clk Pulse Duration, Low
100 77 100 6.5 - 0.0 8.0 - 0.0 - 6.5 - - - - 5.0 5.0
)
133 200 3.5 - 0.0 4.5 - 0.0 - 3.5 - - - - 2.5 2.5
Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section.
Table 2-0030A/2064E
5
Specifications ispLSI 2064E
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER Inputs #
2
DESCRIPTION
-200
-135
-100
MIN. MAX. MIN. MAX. MIN. MAX. - - - - - - - - - 1.2 2.3 - - - - 1.0 - - - - - - - 0.7 0.9 - 0.5 1.1 0.6 1.4 1.9 2.9 2.9 2.9 0.5 - - 0.3 0.6 4.3 4.9 4.0 0.9 0.4 1.6 1.5 2.0 2.0 2.0 0.7 0.9 3.4 - - - - - - - - - 0.7 4.3 - - - - 2.5 - - - - - - - 1.6 1.8 - 0.5 1.7 1.2 3.7 4.2 5.2 5.2 5.2 0.5 - - 0.3 1.1 6.0 6.9 5.5 1.0 0.5 1.6 1.5 3.4 3.4 3.6 1.6 1.8 6.3 - - - - - - - - - 1.2 4.0 - - - - 4.1 - - - - - - - 2.7 2.7 - 0.5 2.2 1.7 5.8 5.8 6.8 7.3 8.0 0.5 - - 0.3 1.3 6.1 8.6 7.1 1.4 0.4 1.6 1.0 4.2 4.2 4.8 2.7 2.7 9.2
UNITS
tio tdin
GRP
20 Input Buffer Delay 21 Dedicated Input Delay 22 GRP Delay 23 4 Product Term Bypass Path Delay (Combinatorial) 24 4 Product Term Bypass Path Delay (Registered) 25 1 Product Term/XOR Path Delay 26 20 Product Term/XOR Path Delay 27 XOR Adjacent Path Delay 3 28 GLB Register Bypass Delay 29 GLB Register Setup Time before Clock 30 GLB Register Hold Time after Clock 31 GLB Register Clock to Output Delay 32 GLB Register Reset to Output Delay 33 GLB Product Term Reset to Register Delay 34 GLB Product Term Output Enable to I/O Cell Delay 35 GLB Product Term Clock Delay 36 ORP Delay 37 ORP Bypass Delay 38 Output Buffer Delay 39 Output Slew Limited Delay Adder 40 I/O Cell OE to Output Enabled 41 I/O Cell OE to Output Disabled 42 Global Output Enable 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 45 Global Reset to GLB
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tgrp
GLB
t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck
ORP
torp torpbp
Outputs
tob tsl toen todis tgoe
Clocks
tgy0 tgy1/2
Global Reset
tgr
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/2064E
6
Specifications ispLSI 2064E
ispLSI 2064E Timing Model
I/O Cell
GRP Feedback
GLB
ORP
I/O Cell
Ded. In
#21 I/O Delay #20 GRP #22
Comb 4 PT Bypass #23 Reg 4 PT Bypass #24 20 PT XOR Delays #25, 26, 27 D RST GLB Reg Bypass #28 GLB Reg Delay Q #29, 30, 31, 32 ORP Bypass #37 ORP Delay #36 #38, 39 I/O Pin (Output)
I/O Pin (Input)
Reset
#45
Control RE PTs OE #33, 34, CK 35 Y0,1,2 GOE 0,1 #43, 44 #42
#40, 41
0491/2064
Derivations of tsu, th and tco from the Product Term Clock tsu
= = = 3.1ns = = = = 3.4ns = = = = 7.9ns = Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.5 + 0.6 + 2.9) + (1.2) - (0.5 + 0.6 + 1.0) Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.5 + 0.6 + 4.0) + (2.3) - (0.5 + 0.6 + 2.9) Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.5 + 0.6 + 4.0) + (0.3) + (0.9 + 1.6)
Table 2- 0042A-2064e
th
tco
Note: Calculations are based upon timing specifications for the ispLSI 2064E-200L.
7
Specifications ispLSI 2064E
Power Consumption
Power consumption in the ispLSI 2064E device depends on two primary factors: the speed at which the device is operating and the number of Product Terms used. Figure 3. Typical Device Power Consumption vs fmax
160 150 140 130
Figure 3 shows the relationship between power and operating speed.
ispLSI 2064E
ICC (mA)
120 110 100 90 80 70 1 20 40 60 80 100 120 140 160 180 200
fmax (MHz)
Notes: Configuration of Four 16-bit Counters Typical Current at 5V, 25 C
ICC can be estimated for the ispLSI 2064E using the following equation: ICC(mA) = 7 + (# of PTs * 0.75) + (# of nets * Max freq * 0.004) Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
0127A/2064E
8
Specifications ispLSI 2064E
Pin Description
NAME
I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 I/O 32 - I/O 35 I/O 36 - I/O 39 I/O 40 - I/O 43 I/O 44 - I/O 47 I/O 48 - I/O 51 I/O 52 - I/O 55 I/O 56 - I/O 59 I/O 60 - I/O 63 GOE 0, GOE 1 Y0, Y1, Y2 RESET BSCAN
TQFP PIN NUMBERS
17, 21, 29, 33, 40, 44, 48, 56, 67, 71, 79, 83, 90, 94, 98, 6, 66, 11, 15 14 18, 22, 30, 34, 41, 45, 53, 57, 68, 72, 80, 84, 91, 95, 3, 7, 87 65, 62 19, 23, 31, 35, 42, 46, 54, 58, 69, 73, 81, 85, 92, 96, 4, 8, 20, 28, 32, 36, 43, 47, 55, 59, 70, 78, 82, 86, 93, 97, 5, 9
DESCRIPTION
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
Global Output Enable input pins. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Active Low (0) Reset pin which resets all of the registers in the device. Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK options become active. Input - This pin performs two functions. When BSCAN is logic low, it functions as an input pin to load programming data into the device. TDI/IN0 also is used as one of the two control pins for the JTAG state machine. When BSCAN is high, it functions as a dedicated input pin. Input - This pin performs two functions. When BSCAN is logic low, it functions as a pin to control the operation of the JTAG state machine. When BSCAN is high, it functions as a dedicated input pin. Output/Input - This pin performs two functions. When BSCAN is logic low, it functions as an output pin to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin. Input - This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the Serial Shift Register. When BSCAN is high, it functions as a dedicated input pin.
TDI/IN 02
16
TMS/IN 12 TDO/IN 22
37 39
TCK/IN 32
60
GND VCC VCCIO NC1
2, 51, 12, 1, 10, 50, 89,
13, 63, 64 24, 26, 61, 99,
25, 74,
38, 88
Ground (GND) VCC
52, 27, 76, 100
75 49, 77,
Supply voltage for output drivers, 5V or 3.3V. All VCCIO pins must be connected to the same voltage level. No Connect.
1. NC pins are not to be connected to any active signals, VCC or GND. 2. Pins have dual function capability.
Table 2-0002-2064E.eps
9
Specifications ispLSI 2064E
Pin Configuration
ispLSI 2064E 100-Pin TQFP Pinout Diagram
NC1 NC1 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 NC1 GND GOE 1 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 NC1 NC1
VCCIO GND I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 1NC Y0 VCC GND BSCAN RESET 2TDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 VCCIO GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
ispLSI 2064E
Top View
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VCCIO GND I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 GOE 0 Y1 VCC GND Y2 NC1 TCK/IN 32 I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 VCCIO GND
1NC
1NC
I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 2TMS/IN 1 GND 2TDO/IN 2 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 1NC 1NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
0766A-2064E
1. NC pins are not to be connected to any active signals, VCC or GND. 2. Pins have dual function capability.
10
Specifications ispLSI 2064E
Part Number Description
ispLSI 2064E - XXX X
Device Family Device Number Speed 200 = 200 MHz fmax 135 = 135 MHz fmax 100 = 100 MHz fmax Package T100 = TQFP Power L = Low
0212/2064E
XXXX X
Grade Blank = Commercial
ispLSI 2064E Ordering Information
COMMERCIAL
FAMILY ispLSI fmax (MHz) 200 135 100 tpd (ns) 4.5 7.5 10 ORDERING NUMBER ispLSI 2064E-200LT100 ispLSI 2064E-135LT100 ispLSI 2064E-100LT100 PACKAGE 100-Pin TQFP 100-Pin TQFP 100-Pin TQFP
Table 2-0041A/2064E
11

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